The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
Modern integrated circuits can be made up of literally millions of active devices, such as transistors, capacitors, and the like. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective semiconductor wafer or “chip.” Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or so-called “flip-chip” bonding. As known in the art, a flip chip, also known as a controlled collapse chip connection or its acronym, “C4,” is a method for interconnecting semiconductor devices, such as integrated circuit chips and micro-electromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is “flipped” over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry.
Structurally, a solder bump actually contains the bump itself and a so-called under-bump-metallurgy (UBM) located between the bump and a pad. An UBM generally contains an adhesion layer, a barrier layer, and a wetting layer, arranged in that order, on the pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps, and bumps with mixed metals. In copper pillar bump technology, instead of using a solder bump, the electronic component is connected to a substrate by means of a copper pillar bump (or more simply copper pillar), which achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits, and allows the electronic component to perform at higher frequencies.
In current practice, during wet etching of the UBM copper layer or bump in accordance with some fabrication steps, an isotropic etch profile is produced, in which the etching is at the same rate in all directions, leading to undercutting of the etched copper bump. This action results in an undesirable loss of copper pillar width. The undercut caused by the wet etching process will also induce undesirable stresses in the copper pillar, possibly resulting in bump sidewall delamination and bump cracking. Although the undercut is an inherent result of the etching process, the undercut is detrimental to the long-term reliability of the interconnection. The undercut compromises the integrity of the solder bump structure by weakening the bond between the solder bump and the bonding pad of the chip, thereby leading to premature failure of the chip.
Accordingly, it is desirable to provide improved methods for fabricating integrated circuits that include copper layers, such as copper bumps. It further is desirable to provide methods for fabricating integrated circuits that avoid undercutting the copper bump during etching of one or more of the copper layers. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.